The present invention relates to circuits and methods for controlling integrated circuit power consumption, and particularly, to circuits and methods incorporating phase change switches.
Power consumption increasingly has become a major obstacle to circuit and system designers. Advances in integrated circuit (IC) technology have resulted in millions of transistors being placed on single ICs. Additionally, IC technology advances have enabled circuits to switch at increasingly faster speeds. As the physical sizes of ICs continue to shrink while at the same time performance (i.e. switching speed) increases, power density substantially increases. This substantial increase in power density causes power management problems for system designers. Power management problems may be manifested in various forms such as, for example: heat dissipation, battery life, performance, and reliability. As the amount of power dissipated by conventional ICs increases while chip area decreases, significant thermal control issues at the system level arise. The problem has become so pervasive that conventional forced air cooling systems are no longer able to dissipate the power generated by modern ICs. System designers are required to utilize liquid cooled solutions for handling ever increasing power dissipation requirements. Increased power consumption also creates battery life issues in portable systems and can significantly impact the usefulness of portable devices.
Conventional circuit techniques for reducing power consumption in integrated circuits typically comprise the use of transistors as switches for isolating one or more blocks of logic from power sources. When the logic block(s) is in use, the switches are closed, thus coupling the logic block to the power sources. When the logic block(s) is not in use (e.g. low power or standby mode), the switches are opened, thus decoupling the logic block(s) from the power sources. Various transistor switch-based circuit techniques for reducing power consumption are well known in the art. For example, U.S. Pat. No. 6,693,484 (the '484 patent) assigned to The Regents of The University of California on Feb. 17, 2004, entitled “Low-power high-performance integrated circuit and related methods” discloses such conventional circuitry. For example, FIG. 1 of the '484 patent illustrates two isolation transistors Q1 and Q2 that are positioned between a logic block (e.g. an inverter circuit) and power and ground sources, respectively, and couple the logic block to those sources. When the logic block is to be activated, control signals switch both Q1 and Q2 on, thus activating the logic block. When the logic block is to be deactivated, control signals switch both Q1 and Q2 off, thus isolating the logic block from the power and ground sources, respectively, thereby deactivating the logic block.
There have been shortcomings with conventional transistor switch-based power reduction techniques. Mainly, leakage current is generated when the isolation transistors decouple the logic block(s) from the power sources. This leakage current is directly proportional to the off impedance of the isolation transistor. The off impedance of a typical FET transistor is approximately 1×107 Ohms/um. In certain applications, such as low power and thermally sensitive applications, such an off impedance value may not be sufficient, Additionally, as the density of ICs continues to rise, and thus more transistors can be placed on a chip, the off-state leakage current associated with de-activated circuits can increase to the point of limiting or even inhibiting the operation of the system in which the IC resides. Thus, it would be desirable to use a switch-based circuit technique for reducing power consumption where the switch mechanism has a higher off impedance as compared to conventional transistors.
Additionally, the size of conventional isolation transistors must be very large to accommodate source/sink currents. The amount of source/sink current is directly proportional to the on impedance value of an isolation transistor. The on impedance of atypical FET transistor is approximately 600 Ohms/um. The size (i.e. width) of an isolation transistor is determined by the amount of current required by the logic block to which the transistor is coupled when the logic block is active. Thus, the greater the current demand, the larger the isolation transistors must be to accommodate that demand. Conventional integrated circuit designs require very large isolation transistors in order to accommodate high current load requirements. Large transistors negatively impact the overall size of an IC. Additionally, as the density of ICs continues to rise, and thus more transistors can be placed on a chip, more isolation transistors may be required for power management purposes, thus having a greater negative impact on the size of ICs. Thus, it would be desirable to use a switch-based circuit technique for reducing power consumption where the switch mechanism has a lower on impedance as compared to conventional transistors.